San Jose, Calif., —November 12, 2015—Altera Corporation (NASDAQ: ALTR) is demonstrating FPGA acceleration using its leading-edge FPGAs and SoCs at Supercomputing 2015 (Booth 462), being held November 15 to 20 at the Austin Convention Center, Austin, Texas. Altera will demonstrate how the Altera® software development kit (SDK) for Open Computing Language (OpenCL™), combined with its portfolio of FPGAs and SoCs, can help designers achieve high-performance, power-efficient system acceleration. Altera’s Michael Strickland, director in the Computer and Storage business, will also appear on a panel: SC15: Reconfigurable Supercomputing on Tuesday, November 17, from 5:30-7:00 p.m., in room 16AB.
The Altera SDK for OpenCL is a game-changer that offers programmers familiar with C programming a design environment that “abstracts away” the traditional FPGA development environment. It can be used to easily program the industry’s first 1.5 TFLOP-capable FPGA, Arria™ 10, and other Altera FPGAs and SoCs.
System designers using FPGAs can create applications that accelerate servers in the data center and cloud to power applications, including online search and facial recognition, deep-learning neural networks, security, genomics research, video processing, and many more high performance computing (HPC) applications. FPGAs provide users with an accelerator that delivers a cost, power, and performance benefit over other solutions for scalable high-performance computing.
Altera in-booth demonstrations include:
- Altera Arria 10 FPGAs offering the industry’s first 1.5-TFLOP IEE754-conformant FPGA, demonstrating single-precision floating-point matrix multiply operations
- Altera FPGA accelerators used to perform deep-learning and neural networking for facial detection and recognition
- Advanced 3D video processing featuring Gidel’s FPGA-based reconfigurable technology
- A Snort application for cyber security running on an Altera Arria 10 FPGA, showing a 100X to 200X performance gain over today's state-of-the-art servers
- 25/40GbE low-latency TCP offload to an Altera Arria 10 FPGA
