On November 19 and 21, 2019 Lattice Semiconductor's Hussein Osman, Consumer Segment Manager, and Hoon Choi, Fellow and Head of AI/ML development, will co-present two sessions of a free one-hour webinar, "Delivering Milliwatt AI to the Edge with Ultra-Low Power FPGAs," organized by the Embedded Vision Alliance. The first session will take place at 11 am PT (2 pm ET) on the 19th, timed for attendees in the Americas. The second session, at 6 am PT (3 pm Central European Time) on the 21st, is schedule-tailored for attendees in Europe.
Products with embedded artificial intelligence (AI) capabilities are increasingly being developed for smart home, smart city, and smart factory applications. Low power FPGAs are proving to be well suited for implementing machine learning inferencing at the edge, given their inherent parallel architecture. By combining ultra-low power, high performance, programmability and comprehensive interfaces support, these low power FPGAs give edge device developers the flexibility they need to address changing design requirements, including the ability to adapt to evolving deep learning algorithms and architectures.
Lattice's iCE40 UltraPlus and ECP5 product families support development of Edge AI solutions that consume anywhere from 1 mW to 1 W on compact hardware platforms. To accelerate development, Lattice has also brought together the award-winning sensAI stack, which gives designers all of the tools they need to develop low power, high performance Edge devices.
The first section of this webinar explores the sensAI stack, various system-level architectures to implement smart edge devices, and Lattice's end-to-end reference design flow that simplifies the implementation of target applications, including security and smart cameras, human-to-machine interfacing using voice and gesture, and object identification. The focus then shifts to memory management techniques, quantization and fractional settings used for deployment of small models on low power edge devices. Performance and power metrics are provided for common use cases, and are also compared against other hardware implementation options such as MCUs.
Everyone who registers for the webinar and attends the webinar live will earn the chance to win one of ten Himax HM01B0 UPduino Shields, based on Lattice’s iCE40™ UltraPlus FPGA. Winners will be notified via email on December 16th.
For more information and to register for this free webinar, please see the event page for the first session at 11 am PT on November 19th or the second session at 6 am PT on November 21st (please make sure you sign up for the correct one!). For more information, please email [email protected].
UPDATE: Now that the live webinar is over, see here (first session) and here (second session) for the on-demand archive.
