This market research report was originally published at the Yole Group’s website. It is reprinted here with the permission of the Yole Group.
ECTC explores integration, bonding technologies and new materials in search of advanced packaging for the AI age
Advanced packaging is a linchpin for the semiconductor industry which is wrestling with integrating multiple dies in a single package. Stefan Chitoraga and Gabriela Pereira, both Technology and Market Analysts specialized in advanced packaging at Yole Intelligence, part of Yole Group, and Belinda Dube, Technology & Cost Analyst at Yole SystemPlus, also part of Yole Group, reflect on some of the technology trends discussed at the recent ECTC (Electronics Components and Technology Conference) designed to meet the needs of AI, networking, autonomous vehicles, high-end PCs and gaming.
The advanced packaging market continues to be resilient despite an economic downturn in the broader economy. Yole Group’s most recent Advanced Packaging Market Monitor records a revenue increase of around 10% in 2022, compared to the previous year. It was worth US$44.3 billion in 2022 and is expected to realize a Compound Annual Growth Rate (CAGR) of 10.6% from 2022 to 2028 and reach US$78.6 billion by 2028.
The high-end performance packaging, used to integrate dies with more advanced nodes, is expected to surpass US$16 billion in 2028, representing more than 20% of the advanced packaging sector. Among different advanced packaging platforms, 2.5D/3D is the fastest growing, with a CAGR close to 40% between 2022 and 2028. It is one of the most analyzed and developed technologies, accounting for the large CAGR in revenue.
Chiplets and heterogeneous integration revolutionize advanced packaging
“With the slowdown of Moore’s law and as leading-edge nodes increase in complexity and cost, advanced packaging is becoming a crucial solution to integrate multiple dies in a single package, with the possibility to combine mature and advanced nodes. Heterogeneous integration and chiplet-based approaches are becoming necessary in market segments such as AI, networking, autonomous driving, high-end PCs and high-end gaming. Heterogenous integration through advanced packaging technologies enables cost-effective multichip integration within a compact floorplan, enabling a superior performance compared to conventional packaging.”
Stefan Chitoraga
Technology and Market Analyst, Advanced Packaging, Yole Intelligence (part of the Yole Group)
Integrating a higher number of active circuits inside the package is one way to distribute different functions into different chips integrated into the same package via dense interconnects. Time-to-market is also reduced because chips can be from different manufacturers and assembled.
Hybrid bonding is everywhere
Several sessions at ECTC were dedicated to hybrid bonding. It is becoming key in the advancement of assembly technologies within the heterogeneous integration and chiplet space, because it allows a high-density vertical stack of different dies inside a package.
“Hybrid bonding can be wafer-to-wafer, die-to-wafer or die-to-die. Its leading advantage is that it allows 3D device stacking for vertical scaling and a higher interconnection density than other die stacking technologies. It is also characterized by a fine pitch bonding leading to a higher interconnection density. This also increases the system bandwidth and power efficiency. Speed is also increased because conventional bumps are eliminated and direct copper-to-copper bonding is used instead. This creates a very close interconnect and as the bonding pads are part of the die structure, it increases the bonding strength and reliability.”
Belinda Dube
Technology and Cost Analyst, Yole SystemPlus (part of the Yole Group)
Some speakers talked about developments that can be made to improve hybrid bonding technologies, for example enhancing the bonding strength. There is also room to improve yield. Contamination issues also blight hybrid bonding; while risk of contamination is not higher than other technologies, the impact of a particle preventing transmission is greater because of the fine pitches.
The viability of glass
As well as new technologies, there were also discussions on new materials at ECTC.
“Glass is emerging as one of the key materials that could be used in a package. It has many advantages, such as a high thermal conductivity, mechanical strength, low dielectric constants and low dielectric loss. It also has the ability to create fine lines and spaces, allowing for small pitches, and a CTE (coefficient of thermal expansion) which is closer to silicon than the other organic materials typically used in packaging.”
Gabriela Pereira,
Technology and Market Analyst, Advanced Packaging, Yole Intelligence (part of the Yole Group)
It is already becoming popular in RF, HPC, photonics and CPO (co-packaged optics) applications.
ECTC attendees saw developments around glass substrates and glass interposers, including Georgia Tech working in close collaboration with glass suppliers and IC substrate suppliers to develop reliable and high-performance solutions.
One area being developed is glass core substrates to replace the traditional IC substrate’s organic core. This could be used, principally, in HPC and RF applications.
In addition to a lower cost compared to silicon, glass has many benefits. It allows the integration of chips in large packages while providing a better flatness, which is crucial for HPC and AI applications. Its low dielectric constant will be vital when frequencies increase beyond 5G, when 6G and 7G will increase frequencies once more.
Challenges around building IC substrates with glass core and replacing silicon interposers with glass ones are related to the weight of the glass and to the CTE difference between the glass and organic layers around the core that could impact the package reliability.
Another issue is that metallization processes to build traces is more difficult than in silicon. This is, however, a relatively small issue and one that is likely to solved.
Companies like Japanese materials provider Hoya, and USA’s Corning and Schott are interested in getting into this sector.
To date, there is no high-volume manufacturing, and the integration of glass in packaging is unlikely for some years as some ongoing challenges still need to be solved., Nevertheless, it is reported that glass substrate supplier Absolics is expected to begin small volume production of glass core IC substrates later this year or in early 2024.
Co-Packaged Optics (CPO) is becoming a reality
Another trend, CPO, is relevant to the networking and data center market where demand for increased bandwidth is driving the development of photonic interconnections for speed and lower power consumption.
CPO is packaging electronics and a photonic chip, for example an ASIC or CMOS die interconnected with a photonic chip. This area sees companies collaborating: there were presentations from networking and data center, chip suppliers, foundries, OSATs, R&D institutes and materials suppliers at ECTC. Many are looking at advanced substrates where the interconnection between the two chips is achieved through the IC substrate.
There were also presentations referring to a fan-out packaging approach while others looked into glass substrates. In addition, there was also a variety of interconnection technologies discussed. Microbumps, TSVs, RDLs, silicon bridges and silicon interposers are all experiencing technology improvement.
Forging a local advanced packaging supply chain: efforts and challenges ahead
In the last years, the semiconductor supply chain has been hit by Covid-19, chips and materials shortages and the invasion of Ukraine by Russia. This has caused disruption at various and started to trigger local governments to invest in domestic production of semiconductors.
At ECTC, the CHIPS Act efforts to bring Advanced Packaging to North America were discussed. The strong collaboration and partnerships between different elements of the domestic supply chain are observed and these encompass design, device makers, material and equipment suppliers, R&D institutes and even OSATs.
Apart from enabling more advanced packaging R&D activities in the US, one of the goals is to support the migration from R&D to manufacturing and commercialization, but companies agree that more cleanroom space is needed which requires infrastructure investment. This also takes time. In the US, high labor costs, a skills shortage and the need for funding are still hampering the domestic supply chain. In Europe, the same factors apply.
Heterogeneous integration enabled by advanced packaging is driven by the fact that it is more costly and more difficult to produce advanced front-end nodes today. Historically, packaging was an OSAT business, and they are still very important in this domain, but it is TSMC and IDMs, such as Samsung and Intel, proposing since last decade advanced back-end solutions as well as using their front-end capabilities for 2.5D or 3D solutions such as silicon interposers, silicon bridges and hybrid bonding.
Performance levels to meet the system requirements of digitization, the rise of AI, and the increasing needs in networking, 5G and autonomous vehicles cannot be met just by decreasing silicon nodes because of the associated cost and yield penalties. Attention is therefore on advanced packaging to integrate together dies from advanced or and mature nodes to reduce system cost.
Advanced packaging and, specially, high-end performance packaging will rely on overcoming challenges around placing multiple dies in the same package, enhancing the pitch, interconnection density and the bandwidth between dies.
The industry is therefore looking to heterogeneous integration and hybrid bonding, but also researching new materials for cost-efficiency and improved performance and new technologies such as CPO to move advanced packaging to the next level to meet the next generation of performance demands.
