This market research report was originally published at the Yole Group’s website. It is reprinted here with the permission of the Yole Group.
Yole Group anticipates strong growth in the PLP market with a 27% CAGR from 2024 to 2030, driven by its cost efficiency and ability to meet both advanced and traditional packaging needs.
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Market metrics: from about $160 million to more than $600 million, the PLP (1) market points at a 27% CAGR (2) during the 2024-2030 period. By 2030, high-density fan-out and ultra-density platforms will dominate the market in response to the AI (3) push.
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Ecosystem: in 2024, the PLP market is led by Samsung Electronics, closely followed by STMicroelectronics. Following them, other companies, including PTI, SIPLP, ASE…, have market shares of less than 10%.
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PLP is a cost-efficient solution for advanced packages that are today manufactured at the wafer level, including WLCSP (4), fan-out, and 2.5D organic interposers. PLP can also be utilized to replace traditional packaging technologies like lead frame QFN (5).
Yole Group expects significant growth for the PLP market from 2024 to 2030, with a 27% CAGR. More PLP capacity is being installed, and the market is growing robustly, though it still generates a relatively small portion of the advanced packaging revenue.
PLP is a cost-efficient solution for advanced packages manufactured today at the wafer level, explains Yole Group in its new Panel Level Packaging 2025 report. PLP solutions include WLCSP, fan-out, and 2.5D organic interposers.
“Apart from advanced packaging, PLP can replace traditional packaging technologies like lead frame QFN, addressing small, simple packages for applications like RF electronics components, power electronic modules, and MCUs.”
Gabriela Pereira
Technology and Market Analyst, Semiconductor Packaging, Yole Group
The Panel Level Packaging 2025 report delivers a comprehensive exploration of the fast-evolving PLP landscape, offering in-depth analysis of the technologies, market drivers, and application trends shaping the industry. This new report on semiconductor packaging by Yole Group identifies and classifies PLP technologies and analyzes both high-end applications for AI and HPC6 and low-end trends replacing QFN in power and analog segments. Moreover, analysts provide a detailed PLP benchmark versus wafer-level packaging in terms of cost and area efficiency. They outline the major technology roadmaps and provide a detailed overview of the global and Chinese PLP supply chains. Forecasts are segmented by package type, technology type, carrier size, and material.
Fan-In PLP production ramped up in 2024, capturing about a third of the PLP market, while core Fan-Out and HD Fan-Out captured the remaining two-thirds. The UHD Fan-Out segment of PLP has not yet been commercialized, however Yole Group expects low-volume production to start soon, driven by AI/HPC and high-end PC.
“Indeed, we expect TSMC to start running some PLP prototypes in the next few years, as it has recently started developing the technology”
Yik Yee TAN, PhD
Senior Technology and Market Analyst, Semiconductor Packaging, Yole Group
PLP players have been focusing on developing technology for one of the two segments: low-end fan-out/fan-in PLP or high-end fan-out PLP. In terms of revenue, high-end, large-size FOPLP is the largest driver in the PLP market.
Fueled by chiplets and heterogeneous integration, semiconductor package sizes will continue to grow in the coming years. High-end packages for servers and data center AI applications currently feature the largest package dimensions. Therefore, they incorporate large-sized IC substrates and different flavors of 2.5D interposers. To achieve the desired system performance while remaining cost-efficient, the integration of more chiplets and memory is essential. However, as interposer sizes increase, fewer chips can be produced per wafer.
This trend pushes the industry to transition from silicon to organic interposers and reconsider the wafer-level packaging paradigm, potentially adopting larger carrier platforms like PLP. For a large package size of ~5.5x the reticle size limit, PLP can increase carrier area efficiency by more than 80%, whereas WLP only allows 45%. In the Panel Level Packaging 2025 report, Yole Group’s analysts estimated that PLP for UHD FO packages could enable a cost reduction of 10% to 20%, depending on the panel size utilized.
With expertise spanning materials, device manufacturing, and equipment, Yole Group covers key advanced packaging platforms. As a trusted industry partner, they continue to drive knowledge and innovation in the field.
Acronyms
[1] PLP: Panel-Level Packaging
[2] CAGR: Compound Annual Growth Rate
[3] AI: Artificial Intelligence
[4] WLCSP: Wafer-Level Chip-Scale Packaging
[5] QFN: Quad Flat No-Lead package
[6] HPC: High-Performance Packaging
